Assignment Description
- You have a solid background with experience of ASIC development.
- Used to work with complex ASIC and/or large FPGA design.
- Multi clock domains.
- System Verilog.
- Good English skills, in both speech and writing.
- Parameterized IP block design.
- Experience in SOC/DSP architecture.
- Experience in packet based communication protocol.
Desired Skills
- Experience of systemization and architecture design.
- Backend work with timing constraints, timing optimization and formal verification.
- UVM verification.
- Scripting skills.
- Telecom.
- Simulation (Xcelium).
- GIT.
- Linting tools (Spyglass, etc).
- Scripting skills (Python, shell script, tcl).
